With Effect From the Academic Year 2013-14

BIT 431                                            

VLSI DESIGN LAB

Instruction                                                                                                         4 Periods per week
Duration of University Examination                                                                  3Hours
University Examination                                                                                     75Marks
Sessional                                                                                                            25 Marks

1. Switch level modeling usingVerilog
        a) Logic gates  b) AOland OAI gates
        c) Transmission gate d) Complex logic gates using CMOS

2. Structural Gate-levelModeling[With and Without delays]—Digital circuits using gate primitives—usingVerilog.
         a)AOl gate b) Half adder and full adders
         c) MUX using buffers d) S-R latch etc.

3. Mixed gate —level and Switch-level modeling usingVerilog-usage.ofprimitives, modules and instancing and understanding the hierarchical design.
       a) Constructing a 4-input AND gate using CMOS 2-input NAND and NOR gates.
       b) Constructing a decoder using CMOS 2-input AND gates and NOT gates etc.

4. RTL Modeling of general VLSI system components.
    a) MUXes b) Decoders c) Priority encodes d) Flip-flops e) Registers.

5. Synthesis of Digital Circuits
    a) Ripple carry adder and carry look-ahead adder
    b) array multiplier

6.        Verilogcode for finite state machine

7.        Modeling of MOSFET

8.        Stick diagram representations.Simple layouts of Inverter.Understanding the concepts of Design Rule checking.

9.        Fault Modeling for Stuck-at-O and Stuck-at-I faults.

10.      Clock generation circuits (study)