With Effect From the Academic Year 2013-14

BIT 410

CPLD AND FPGA ARCHITECTURE

(ELECTIVE –III)

Instruction  per Week                                                                                                4 Periods
Duration of University Examination                                                                                3 Hours
University Examination                                                                                              75 Marks
Sessional                                                                                                               25 Marks

UNIT – I

Review of Logic Design, Implementation with NAND – NOR gates, designing with multiplexers, implementation of logic functions with look-up tables, minimization of combinational functions based on a) Circuit size, gates and literals i.e. space & power b) number of levels of logic i.e. time or circuit depth.

The Quine-McCluskey Algorithm, Multi level logic minimization, covering, factored forms, technology mapping, review of finite state machines, one hot encoding

UNIT – II

Programmable Logic: Introduction, programmable logic devices (PLDs), SPLDs, CPLDs, fundamentals of PLD circuits, PLD symbology, PLD architectures: Progrmmable Read Only Memories (PROMs), Programmable Array Logic (PAL), ALTERA CPLDs

UNIT – III

FPGAs: Introduction, Programming Technologies: SRAM, Antifuse, EPROM and EEPROM Xilinx FPGAs, Actel, Altera, Concurrent Logic FPGAs. Crosspoint Solutions FPGA, translation to XNF format, Partition, Place and route, Technology mapping for FPGAs: Logic Synthesis, logic Optimization, Lookup Table Technology Mapping, Mapping into Xilinx 3000 CLBs, Multiplexer Technology, Mapping.

UNIT – IV

Logic Block Architecture: Logic Block functionality Versus area-efficiency, Impact of Logic Block Functionality in FPGA performance, Routing for FPGAs: Segmented Channel Routing, Routing for Symmetrical FPGAs, CGE detailed router Algorithm. Flexibility of FPGA routing architectures: Logic Block, Connection Block, Trade offs in Flexibilities of the S and C blocks, A theoretical model for FPGA routing.

UNIT – V

Platform FPGA architectures, Multi-FPGA Systems: Xilinx Virtex II Pro Platform FPGA, Altera Stratix Platform FPGA, Serial I/O, Memories, CPUs and Embedded Multipliers, Multi FPGA systems: Interconnecting Multiple FPGAs, partitioning, Novel architectures.

Suggested Reading:

1.Park K. Chan / Samiha Mourad, “Digital Design using Field Programmable Gate Arrays”, Pearson, 1994 (Unit-I)

2.Ronald J Tocci, Neal S. Widmer, Gregory L. Moss, “Digital Systems: Principles & Applications”, 10^th Edition, Pearson, 2009 (Unit-II)

3.Stephen Brown Zvonko Vranesic – Fundamentals of Digital Logic with VHDL design, McGraw Hill – 2000 (Unit I & II).

4.Stephen D. Brown, Robert J Francis, Jonathan Rose, Ivonko G. Vranesic, “Field Programmable Gate Arrays”, Springer International Edition, First Indian Print 2007(Unit III & IV)

5.Wayne Wolf, “FPGA-based System Design”, Pearson Education, First Impression, 2009 (Unit V)

6.Stephen M. Trimberger, “Field Programmable Gate Array Technology” Springer International Edition”, First Indian Reprint 2007.

7.Michel John Sebastian Smith “Application – Specific Integrated Circuits”, Pearson Education, First Indian reprint 2000.