With effect from the academic year 2015-2016
BIT 203
DIGITAL ELECTRONICS & LOGIC DESIGN
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Instruction |
4 |
Periods Per week |
|
Duration of Examination |
3 |
Hours |
|
Univ. Exam |
75 Marks |
|
|
Sessionals |
25 Marks |
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Course Objectives:
- 1.To learn the principles of digital hardware and support given by it to the software.
- 2.To explain the operation and design of combinational and arithmetic logic circuits.
- 3.To design hardware for real world problems.
UNIT – I
Design Concepts – Digital Hardware, Design process, Design of digital hardware Introduction to logic circuits – Variables and functions, Logic gates and networks. Boolean algebra, Synthesis using AND, OR, and NOT Gates, Design examples. Optimized implementation of logic functions – Karnaugh Map, Strategies for minimization, minimizing Product-of-Sum Forms, Incompletely Specified functions, multiple output circuits. NAND and NOR logic networks, Introduction to CAD tools and Very High Speed Integrated Circuit Hardware Description Language (VHDL).
UNIT – II
Programmable logic devices: general structure of a Programmable Logic Array (PLA), gate level diagram, schematic diagram, Programmable Array Logic (PAL) Structure of CPLDs and FPGAs, 2-input and 3-input lookup tables (LUT). Design of Arithmetic-circuits, VHDL for Arithmetic-circuits Combinational circuit building blocks – Multiplexers, Decoders, Encoders, Code converters, Arithmetic comparison circuits. VHDL for Combinational circuits.
UNIT – III
Basic Latch Gated SR Latch, Gated D Latch, Master-Slave and Edge- Triggered D Flip-Flops, T Flip-flop, JK Flip-flop, Excitation tables. Registers-Shift Register, Counters-Asynchronous and synchronous counters, Ring counter, Johnson counter, VHDL code for D Flip-flop and Up-counter
UNIT – IV
Synchronous Sequential Circuits – Basic design steps. Moore and Mealy state model, State minimization, Design of a Counter using the Sequential Circuit Approach. Algorithmic State Machine (ASM) charts
UNIT – V
Asynchronous Sequential Circuits – Behaviour, Analysis, Synthesis, State reduction, State Assignment, examples. Hazards: static and dynamic hazards. Significance of Hazards. Clock skew, set up and hold time of a flip-flop
Suggested Reading:
- 1.Stephen Brown, Zvonko Vranesic, “Fundamentals of Digital Logic with VHDL Design”, 2nd Edition, McGraw Hill, 2009.
- 2.Jain R.P., “Modern Digital Electronics,” 3rd Edition, TMH, 2003.
- 3.John F. Wakerly, “Digital Design Principles & Practices”, 3rd Edition, Prentice Hall, 2001
- 4.M. Morris Mano, Charles R. Kime, “Logic and Computer Design Fundamentals”, 2nd Edition, Pearson Education Asia, 2001.
- 5.ZVI Kohavi, Switching and Finite Automata Theory, 2nd Edition, Tata McGraw Hill, 1995.
- 6.William I Fletcher, “An Engineering Approach to Digital Design”, Eastern Economy Edition, PHI
- 7.H.T. Nagle, “Introduction to Computer Logic”, Prentice Hall,