EFFECT FROM THE ACADEMIC YEAR 2013 - 2014

EC 463

DESIGN OF FAULT TOLERANT SYSTEMS

                                                                  (ELECTIVE –II)

Instruction                                                                                                                                                                                        4  Periods per week

Duration of University Examination                                                                                                                                                   3  Hours

University Examination                                                                                                                                                                    75 Marks

Sessional                                                                                                                                                                                        25 Marks

UNIT-I

Basic concepts of Reliability: Failures and faults, Reliability and failure rate, Relation between reliability & mean time between failure, Maintainability & Availability, reliability of series and parallel systems. Modeling of faults. Test generation for combinational logic circuits :conventional methods (path sesitisation,Boolean difference), Random testing, transition count testing and signature analysis.

UNIT-II

Fault Tolerant Design-I: Basic concepts ,static,(NMR,use of error correcting codes), dynamic, hybrid and self purging redundancy, Sift-out Modular Redundancy (SMR), triple modular redundancy, SMR reconfiguration.

UNIT-III

Fault Tolerant Design-II: Time redundancy, software redundancy, fail-soft operation, examples of practical fault tolerant systems, introduction to fault tolerant design of VLSI chips.

UNIT-IV

Self checking circuits: Design of totally self checking checkers, checkers using m-out of a codes, Berger codes and low cost residue code, self-checking sequential machines, partially self-checking circuits. Fail safe Design: Strongly fault secure circuits, fail-safe design of sequential circuits using partition theory and Berger codes, totally self checking PLA design.

UNIT-V

Design for testable combination logic circuits: Basic concepts of testability, controllability and observability. The Read-Muller expansion technique, level OR-AND-OR design, use of control and syndrome-testing design.