EFFECT FROM THE ACADEMIC YEAR 2013 - 2014
EC 402
VLSI DESIGN
Instruction 4 Periods per week
Duration of University Examination 3 Hours
University Examination 75 Marks
Sessional 25 Marks
UNIT-I
Introduction to HDLs, Basic Concepts of Verilog, Data Types, System Tasks and Compiler Directives.
Gate Level Modeling: Gate Types and Gate Delays. Dataflow Modeling: Continuous assignment and Delays. Design of Stimulus Block.
UNIT-II
Behavioral Modeling: Structured Procedures, Procedural Assignments, Timing control, Conditional statements, Sequential and Parallel Blocks, Generate Blocks. Switch level Modeling.
Tasks, Functions, Procedural Continuous Assignments, Design of Mealy and Moore state models using Verilog.
Logic Synthesis, Synthesis Design flow, Gate level Net list.
UNIT-III
Introduction to MOS Technology, Basic MOS Transistor action: Enhancement and Depletion Modes. Basic electrical properties of MOS, Threshold voltage and Body Effect. Design of MOS inverters with different loads, Basic Logic Gates with CMOS: INVERTER, NAND, NOR, AOI and OAI gates. Transmission gate logic circuits, Bi-CMOS inverter.
UNIT-IV
MOS and CMOS circuit Design Process: MOS Layers, Stick diagrams, Lambda based Design rules and Layout diagrams. Basic Circuit Concepts: Sheet Resistance, Area Capacitance and Delay calculation.
UNIT-V
Combinational Logic: Manchester, Carry select and Carry Skip adders, Crossbar and barrel shifters, Multiplexer.
Sequential Logic: Design of Dynamic Register Element, 3T, 1T Dynamic RAM Cell, 6T Static RAM Cell.
4
D flip flop using Transmission gates. NOR and NAND based ROM Memory Design.
Suggested Reading:
1. Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”, 2/e , Pearson Education, 2008.
2. Michael D. Ciletti, “ Advanced Digital Design with Verilog HDL”,
PHI, 2005.
3. Kamran Eshraghian, Douglas A. Pucknell, and Sholeh Eshraghian,
“Essentials of VLSI circuits and systems”, PHI, 2011.
4. John P. Uyemura, “Introduction to VLSI Circuits and Systems”,
Wiley India Pvt. Ltd., 2011.