WITH EFFECT FROM THE ACADEMIC YEAR 2016 - 2017

EC305                                               

COMPUTER ORGANIZATION AND ARCHITECTURE

Instructions                                                                                         4 Periods per week

Duration of University Examination                                                  3 Hours

University Examination                                                                      75 Marks

Sessional                                                                                             25 Marks

Unit I

Register Transfer Language and Micro operation: Difference between Computer Organization and Architecture, RTL notation, Common bus system using multiplexer and tri-state buffers. Micro-operations: Data transfer, Arithmetic, Logical and Shift.

Basic Computer Organization and design: Computer registers, instruction and interrupt cycle and Design of basic computer. Instruction formats and Addressing modes.

Unit II

Computer Arithmetic: Fixed and floating point numbers: Adders: Binary adder, BCD adder, carry look ahead adder, twos complement adder/subtractor, Multiplication: Booth’s algorithms, its HDL description and Array Multiplier. Division: Restoring and Non-restoring algorithms and their HDL descriptions and Barrel shifter.

Unit III

Control Unit Design: Significance of Control unit, Hardwired Control unit design approach (classical and one-hot methods). Case studies: CPU. Micro-programmed Control unit approach: basic concept, micro-program sequencer.

Unit IV

Input Output and Memory Organization: Input-output interface, Modes of transfer: Programmed I/O, Interrupt I/O and DMA, Priority Interrupt, Input-Output Processor (IOP): CPU-IOP communication

Memory Organization: Memory hierarchy, Main memory: ROM, MROM, EPROM, EEROM, flash memory, RAM types, associative memory (CAM), Cache memory, address mapping techniques, replacement policies, virtual memory.

Unit V

Advances in Computer Organization: RISC, CISC, Parallel processing: Pipeline – Arithmetic and Instruction, Pipeline Conflicts, Flyn’s classification, VLIW architecture.

Processor Performance enhancement strategies: Overlap, Scalar, Super-scalar, Super-pipeline, Instruction Level Parallelism (ILP).

Suggested Reading:

1. Morris Mano M, Computer System Architecture, 3^rd edition, Prentice Hall India, 2007.
2. John P. Hayes, Computer Architecture and Organization, 3^rd edition, McGraw Hill, 1998.
3. William Stallings, Computer Organization and Architecture, Design for Performance, 7^th edition, Prentice Hall India, 2006.