WITH EFFECT FROM THE ACADEMIC YEAR 2016 - 2017

EC306

Digital System Design with Verilog HDL

Instructions                                                                                         4 Periods per week

Duration of University Examination                                                  3 Hours

University Examination                                                                      75 Marks

Sessional                                                                                             25 Marks

Unit I

Introduction to HDLs, Overview of Digital Design with Verilog HDL, Basic Concepts, Data types, System tasks and Compiler Directives. Gate level Modeling, Hierarchical structural modeling. Dataflow modeling. Continuous Assignments, Timing and Delays. Programming Language Interface,

Design of Arithmetic Circuits - Using Vectored Signals, Using a Generic Specification, Nets and Variables, Arithmetic Assignment Statements, Representation of Numbers in Verilog Code, Gate level and hierarchical modeling of 4-bit Binary and BCD adders and 8-bit Comparators.

Verification: Functional verification, simulation types, Design of stimulus block.

Unit II

Switch Level Modeling and examples. Behavioral Modeling: Structured Procedures, Procedural Assignments, Timing Controls, and Conditional Statements, multi-way branching, Loops, Sequential and Parallel blocks, Generate blocks. Tasks, and Functions.

Behavioral/dataflow modeling of basic MSI combinational logic modules: ALUs, Encoders, Decoders, Multiplexers, Demultiplexers, Parity generator/checker circuits, Bus Structure, Reaction Timer,

Static timing analysis, Logic synthesis and Register Transfer Level (RTL) Code.

Unit III

Behavioral/dataflow modeling of sequential logic modules: Latches, Flip Flops, counters and shift registers.

Synchronous Sequential Circuits: Analysis and synthesis of synchronous sequential circuits: Mealy and Moore FSM models for completely and incompletely specified circuits, State Minimization - Partitioning Minimization Procedure, sequence detector.  One-Hot Encoding.

Synthesizable Verilog HDL models fpr sequence detector using Moore and Mealy models, Design of a Modulo-8 Counter using the Sequential Circuit Approach and its verilog implementation. FSM as an Arbiter Circuit.

Unit IV

Algorithmic State Machines (ASMs): ASM chart, ASM block, simplifications and timing considerations with design example. ASMD chart for binary multiplier and Verilog HDL code, one hot state controller.

Asynchronous Sequential logic:  Analysis procedure-Transition table, flow table, race conditions. Hazards with design example of Vending-Machine Controller

Unit V

Memory Devices: Types of memories, RAM BJT cell and 6-T MOS RAM cell, organization of a RAM, Expanding word size and capacity.

Introduction to ASIC’s: Full-custom, standard-cell and Gate array based ASICs. SPLDs: PROM, PAL, GAL, PLA. FPGA and CPLD simplified architecture and applications. ASIC/FPGA Design flow, CAD tools. Combinational circuit Design with Programmable logic Devices (PLDs).

Suggested Reading:

1. 1.Samir Palnitkar, “Verilog HDL A Guide to Digital Design and Synthesis,” 2^nd Edition, Pearson Education, 2006.
2. 2.M. Morriis Mano, Michael D. Ciletti, “Digital Design”, 4^th edition, Pearson Education.
3. 3.Michael John Sebastian Smith, Application Specific Integrated Circuits, Pearson Education Asia, 3^rd edition 2001.

Suggested Reference:

1. 1.Michael D. Ciletti, Advanced Digital Design with the Verilog HDL”, PHI, 2005.
2. 2.J. Bhasker, “A Verilog HDL Primer,” 2^nd Edition, BS Publications, 2001.