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Name: Shilpa B. Darvesh Designation: Asst. Professor Date of birth:22-04-1984 Qualifications: M.Tech, JNTUH, 2013 B.E., OU, 2006 Work Experience: Teaching : 11.5 Years Area of specialization: Embedded Systems and VLSI System Design.
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Subjects taught at U.G Level: Basic Electronics, Electronic Engineering –I, Electronic Devices and Circuits, Pulse ,Digital and Switching Circuits , Electronic Instrumentation, Switching Theory and Logic Design, Advanced VLSI, Circuit Theory,VLSI Design etc. |
Scholastic Performance:
|
Course |
Board/ University |
Specialization (if any) |
Year of Completion |
% of Marks Obtained |
|
S.S.C |
SSC |
|
2000 |
77.16 |
|
INTER/ DIPLOMA |
IPE |
MPC |
2002 |
75 |
|
B. Tech. |
OU |
ECE |
2006 |
65 |
|
M.Tech. |
JNTUH |
ES&VLSID |
2013 |
76.44 |
|
Ph.D |
|
|
|
|
|
If any other |
|
|
|
|
Teaching Experience in the college:
|
S.No |
College |
Designation |
Period |
Experience in years |
|
1 |
MVSR Engineering College |
Asst.Prof. |
08/09/2006 to till date |
12 |
List of Journal Papers Published(from the date of joining in the college):
|
SNO |
Title of the paper |
Vol/Issue/page No/ISSN No |
Month & Year |
National / International |
|
1 |
Design and Implementation of Low power LFSR for fast ATPG process |
Volume 5, Issue 9, pg 75-80 |
September, 2017 |
International |
|
2 |
Enhanced multi threshold Schmitt trigger circuit Design using FINFET Technology |
Vol.04, Issue.08, Pages:0590-0593, ISSN 2322-0929 |
August-2016, |
International |
|
3 |
Fpga Implementation of High Performance Fully Pipelined Aes Algorithm Using Reversible Logic |
Volume 2; Issue 3;Page No. 38-43; ISSN: 2456-043X |
May-June-2016 |
International |
|
4 |
1-Bit Full-Adder cell with Optimized Delay for Energy- Efficient Arithmetic Applications |
Volume 4, Number 1, pp. 1-7, ISSN 0974-2182 |
Dec-2012 |
International |
|
5 |
1-Bit nano CMOS Full-Adder cell for Energy- Efficient Arithmetic Applications |
|
Dec-2012 |
International |
List of Conference Papers Presented (from the date of joining in the college):
|
Sl. no |
Topic |
Venue |
Dates |
|
1 |
Techniques for optimizing power consumption in filp flops -A survey |
MIT college of Engineering, Pune |
15th -16th Dec,2011 |
Professional bodies in which Membership is taken: Indian Science Congress
Number of Conferences/ Workshops/ Seminars attended(from the day of joining in the college):
|
Sl. no |
Topic |
Venue |
Dates |
|
1 |
VLSI Circuits and Systems |
Spoorthy engg. college |
13th -18th Nov, 2017 |
|
2 |
Analog VLSI Design |
CBIT, Hyderabad |
17th & 18th March,2017 |
|
3 |
Signal Processing Techniques |
MVSR Engg. College, Nadergul |
15th to 19th Nov,2016 |
|
4 |
XILINX VIVADO DESIGN SUITE in Association with CoreEL Technologies |
MVSR Engg. College, Nadergul |
22nd & 23rd Sept.,2016 |
|
5 |
Entrepreneurship |
MVSR Engg. College, Entrepreneurship Development Cell , MVSR Engg. College |
30th July,2016 |
|
6 |
Analog and Digital Circuit Design using Cadence |
MVSR Engg. College, ECE Dept. |
12th & 13th January ,2016 |
|
7 |
Digital Image & Video Processing with hands on |
MVSR Engg. College, CSE Dept |
4th to 8th January,2016 |
|
8 |
Intensive Course on Probability Theory & Stochastic Processes
|
MVSR Engg. College, ECE Dept. |
4 - 8 January, 2016 |
|
9 |
Embedded system design & applications hands on |
MVSR Engg. College, IT Dept. |
28th December 2015 to 2nd January,2016 |
|
10 |
Digital Image Processing |
MVSR Engg. College, IT Dept. |
26th to 27th August,2015 |
|
11 |
ANDROID |
Techfort Software Services Pvt. Ltd, Hyderabad MVSREC |
16th July,2015 |
|
12 |
Effective Teaching Skills |
MVSREC |
18th Oct,2014 |
|
13 |
Real Time Implementation of DSP Algorithms using CCS |
Vardhaman College of Engg. Hyderabad |
11-3-2010 |
|
14 |
Information and Communication Technology |
Rajiv Gandhi Institute of Technology, Mumbai |
22-3-2010 & 23-3-2010 |