Scholastic Performance:
Course
|
Board/ University
|
Specialization
(if any)
|
Year of Completion
|
% of Marks Obtained
|
S.S.C
|
BSE
|
|
1995
|
76.3
|
DIPLOMA
|
SBTET
|
ECE
|
1998
|
71.4
|
B.E
|
O.U
|
ECE
|
2002
|
63.7
|
M.E
|
O.U
|
DS
|
2012
|
65.3
|
|
|
|
|
|
|
|
|
|
|
Teaching Experience in the college:
S.No
|
College
|
Designation
|
Period
|
Experience in years
|
1
|
SRI INDU COLLEGE OF NGINEERING
|
Asst.Prof
|
15-04-2006 to 06-05-2007
|
1 Year 1Month
|
2
|
MVSR ENGINEERING COLLEGE
|
Asst.Prof
|
07-05-2007 to Till Date
|
11 Years
|
|
|
|
|
|
|
|
|
|
|
Industrial Experience ( If any):
S.
No
|
Industry/R&D Unit
|
Designation
|
Period
|
Experience in years
|
1
|
BALAJI COMMUNICATIONS
|
Technical Support Executive
|
March 2003 to May 2004
|
1 Year
2 Months
|
2
|
Oracle
|
Technical Support Executive
|
June 2004 to March 2006
|
1 Year
9 Months
|
Achievements/ Awards:
School second rank in S.S.C Board exam
Professional bodies in which Membership is taken: ISCE,IAE
Number of Conferences/ Workshops/ Seminars attended(from the day of joining in the college):
Sl.No
|
Topic
|
Venue
|
Dates
|
1
|
Two Day Training Program On Embedded System Design
|
MVSR ENGG.COLLEGE
|
16th & 17th October,2017
|
2
|
Three Day Intensive Training On Analog, Digital & Mixed Signal VLSI design using Mentor Graphics Tools
|
MVSR ENGG.COLLEGE
|
13th to 15th September 2017
|
3
|
Recent Trends in Network Security with Hands-on Using Network Simulation
|
MVSR ENGG.COLLEGE
CSE&IT Dept.
|
19th to 24th Dec,2016
|
4
|
2-day Faculty Development Program on “ XILINX VIVADO DESIGN SUITE in Association with CoreEL Technologies
|
MVSR ENGG.COLLEGE , Nadergul
|
22nd & 23rd Sept.,2016
|
5
|
2- Day FDP Program on Analog and Digital Circuit Design using Cadence
|
MVSR Engg. College, ECE Dept.
|
12th & 13th
January ,2016
|
6
|
Five day Intensive Course on Probability Theory & Stochastic Processes
|
MVSR Engg. College, ECE Dept.
|
4 - 8 January, 2016
|
7
|
Faculty Development Program of ANDROID
|
Techfort Software Services Pvt. Ltd, Hyderabad MVSREC
|
16th July,2015
|
8
|
Advance Digital Design Using Verilog HDL
|
MVSR Engg. College, Nadergul
|
28th to 31st Jan,2015
|
9
|
Recent Advances in communication Engineering RACE 2008, International Conference
|
ECE Department, O.U
|
20-23
Dec. 2008
|
|