With effect from Academic Year 2015-2016

CS 203          

           LOGIC AND SWITCHING THEORY

Instruction                                                                               4 Periods per week

Duration of University Examination                                      3 Hours

University Examination                                                          75 Marks

Sessional                                                                                 25 Marks

Course objective:

• To introduce number systems and operation of electronic logic elements
• To introduce minimization of Boolean functions and implementation using NAND and NOR Gates.

• To introduce the design of combinatorial and sequential circuits.
• To introduce design of registers and counters.

UNIT-I

Digital Computers and Information: Information representation, Computer Structure.

Number Systems: Binary Numbers, Octal and Hexadecimal Numbers, Number Ranges.

Arithmetic Operations: Conversion from Decimal to other bases. Decimal Codes: BCD Addition. Alphanumeric Codes: ASCII Character Code, Parity Bit.

Binary Logic and Gates: Binary Logic, Logic Gates. Boolean Algebra: Basic Identifiers, Algebraic Manipulation, Complement of a Function.

Standard Forms: Minterms and Maxterms, Sum of Product and Products of Sums.

UNIT-II

Minimization of Switching Functions: Introduction, the map method, Minimal Functions and Their Properties, the tabulation procedure, the prime implicant chart.

NAND and NOR Gates: Nand Circuits, Two-level Implementation, Multilevel NAND Circuits, NOR Circuits. Exclusive OR Gates: Odd Function, Parity Generation and Checking.

UNIT-III

Combination Logic Design: Combinational Circuits, Design Topics: Design Hierarchy, Top –Down design, Computer Aided Design, Hardware Description Languages, Logic Synthesis. Analysis Procedure: Derivation of Boolean Functions, Derivation of the Truth Table, Logic Simulation, Design Procedure, Decoders, Encoders, Multiplexers, Binary Adders, Binary subtraction, Binary Multipliers, HDL Representations- VHDL.

UNIT-IV

Sequential Circuits: Sequential Circuit definitions. Latches, Flip Flops, sequential circuit analysis, sequential circuit design, design with D Flip Flops, designing with JK Flip- Flops, HDL representation for sequential circuits-VHDL.

UNIT-V

Registers and Counters: Registers, Shift registers, Synchronous Binary counters, Ripple Counter.

Symmetric Networks: Properties of Symmetric Functions, Synthesis of Symmetric networks, identification of symmetric functions.

Suggested Reading:

1.M. Moris Mano, Charles R. Kime, Logic and Computer Design Fundamentals, 2nd edition, Pearson Education Asia, 2001.

2.Zvi Kohavi, Switching and Finite Automata Theory, 2nd edition, Tata McGraw Hill, 1995.

3.Charles H. Roth, Jr Fundamentals of Logic Design, 5th edition, Thomson, Brook,Cole, 2005.